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1995 Fools: PowerPC News
From: scherert@mailer.uni-marburg.de (Thomas Scherer) Newsgroups: comp.sys.powerpc Subject: PowerPC News Date: Mon, 03 Apr 1995 11:45:41 +0200 Organization: FB Psychologie Lines: 24 Message-ID: <scherert-0304951145410001@ap0403.psychologie.uni-marburg.de> NNTP-Posting-Host: ap0403.psychologie.uni-marburg.de Date: Mon, 3 Apr 1995 07:43:01 +100 Subject: Re: PowerPC News Priority: high Status: What do you think about this? > > ---------------------------------- > Press Release from 4.1.1995 > > Motorola Inc. and IBM Inc. annouce a brandnew chip design for highest level use. > Under codename "devil" the most sophisticated processor is developed and > production of the PPC 666 ist expected in mid of 1996 in sample sizes. > Short technical info: > 0,28 um chip design with 64 million transistors, speed from 200 to 350 MHz, > 32 stage pipeling, 6 integer, 4 branch predicting and 3 floating point units, > 64 K 8stage assiotiative 1st level cache which use together 16 million > transistors, second chip in same case with 1 MB 2nd level cache (48 million) > with 5 ns access time, together 420..730 SPECint / 370..580 SPECfloat. > Power dissipation 48 W with integratet peltier cooler. > It is expected this chip will beat P7 by factor 3. > > ----------------------------------
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